Silicon, Stack, and Sovereignty: China’s GPU Replacement in the AI Age

硅、栈与主权：AI 时代中国 GPU 国产替代深水记

"The GPU is no longer a graphics card. It is the foundry of thought."

GPU 不再是显卡，它是人类思想重新铸造的熔炉。

When ChatGPT rewrote the rules of software in 2023, and DeepSeek proved in 2025 that a Chinese lab could train a frontier model on non-NVIDIA silicon, the world realized something uncomfortable: AI sovereignty is GPU sovereignty. The country that controls the parallel-compute substrate controls the tempo of the intelligent age.

2023 年 ChatGPT 重写了软件的法则，2025 年 DeepSeek 证明中国团队可以用非英伟达芯片训出前沿模型——世界猛然醒悟：AI 主权即 GPU 主权。谁握住并行计算的底座，谁就握住智能时代的节拍器。

I. The Mirage of “We Can’t Design It”

一、幻象：“我们设计不出来”

The most common misconception in public discourse is that China cannot design a high-end GPU. That is false. By 2026, the paper specs of domestic flagships had already brushed against NVIDIA’s 2022–2023 tier:

中文舆论最大的误判，是以为中国“设计不出高端 GPU”。这是错的。到 2026 年，国产旗舰的纸面参数已经贴住英伟达 2022–2023 档：

Huawei Ascend 910C — 7nm, ~800 TFLOPS FP16, 64GB HBM3, 3.2TB/s, CANN+MindSpore full stack, 384-card CloudMatrix super-node partially out-benchmarking GB200 NVL72 on bandwidth at 4× power.
Biren BR100 — 7nm, 672 TFLOPS FP16, 64GB HBM2e, 2.5D package, once taped out at TSMC before entity-list cutoff, now re-spun domestically at reduced spec.
Cambricon Siyuan 690 — 7nm Chiplet, >700 TFLOPS FP16, 196GB HBM3, 4nm-class dual-die ambition.
MetaX C600 — 128GB HBM3, 3350GB/s, native CUDA-translation layer, 90% scaling at thousand-card scale.
Hygon DCU BW100 — 1.88 PFLOPS FP8, only domestic part passing international SPEC suites, near-zero CUDA porting cost via DTK.

The transistors are drawn. The architecture is not the bottleneck.

电路图画得出来，架构也不是瓶颈。

Design is poetry. Production is engineering. Ecosystem is empire.

设计是诗，制造是工程，生态是帝国。

II. The Four Mountain Passes

二、四座山隘（Where the blood actually spills）

2.1 Process & EUV — the physical ceiling

2.1 制程与 EUV：物理天花板

Training GPUs at H100/B200 class want 4nm/3nm logic, 200B+ transistors, sub-700mm² reticle tricks. SMIC’s N+2 (≈7nm DUV multi-patterning) runs at 40–70% yield depending on metal stack, no EUV in sight, 5nm effectively walled off.

H100/B200 级训练卡要 4nm/3nm、2000 亿+ 晶体管。中芯 N+2（等效 7nm DUV 多重曝光）良率 四到七成，EUV 进不来，5nm 以下基本堵死。每一代工艺代差 ≈ 能效差 30–40%，7×24 训练场景直接变成电费与散热救不回来。

Huawei’s “τ-law” (time-shrink instead of geometry-shrink, targeting equivalent 1.4nm density by 2031 without EUV) is a roadmap, not a product.

华为提的“τ 定律”（用时间缩微替代几何缩微，2031 年无 EUV 拿到等效 1.4nm 密度）目前是路线图，不是现货。

2.2 HBM & CoWoS — the ignored hard wall

2.2 HBM 与 CoWoS：被忽视的硬墙

People blame lithography, but in 2024–2026 the global AI-GPU bottleneck shifted to HBM + 2.5D/3D packaging.

大家骂光刻机，但 2024–2026 年全球 AI GPU 的真实瓶颈已经移到 HBM + 2.5D/3D 封装：

HBM3E/HBM4 locked by SK hynix / Samsung / Micron; CXMT HBM3 samples to Huawei in late 2025, 12-high HBM3E targeted 2027 — 2–3 years behind.
TSV, hybrid bonding, stack yield: every step bleeds.
CoWoS-class silicon-interposer capacity: TSMC ~90% of global, fully booked by NVIDIA/AMD to 2028. Domestic JCET XDFOI / SJ SEMICON wafer-level packages climb the yield curve at 85–98% on smaller interposers, but 5.5-reticle super-interposers + TCB + ABF substrate still partly import-dependent.
A Blackwell needs 8 HBM stacks + 6+ interposers. Drop packaging yield 5% → whole-card BOM explodes.

HBM 堆叠良率掉 5 个点，整卡成本就崩；Blackwell 用 8 颗 HBM、6+ 中介层，封装良率是真钱。

2.3 EDA & SerDes IP — the missing pen

2.3 EDA 与高速 IP：缺的那支笔

7nm-and-below digital full-flow EDA is Synopsys/Cadence/Siemens territory; domestic Empyrean, Primarius cover analog/device-level well but lag on sign-off, thermal-timing co-sim, multi-die DRC.

7nm 以下数字全流程 EDA 被三家垄断，华大九天/概伦在模拟与器件级可用，但 sign-off、热-时序协同、多 die DRC 仍缺位。

HBM PHY, PCIe 6/7, 200G EML optical chips (Lumentum/Coherent ~90% share), PCIe switch (Broadcom monopoly) — domestic substitution <5% in some of these.

HBM PHY、PCIe 6/7、200G EML 光芯片（Lumentum/Coherent 占 90%）、PCIe 交换芯片（博通独占）国产率个位数。

2.4 CUDA — the soft moat that never dries

2.4 CUDA：永不干涸的软护城河

This is the part MBAs underestimate. NVIDIA’s real castle is not the die, it is 20 years × 5.9M developers × 900+ libraries × first-class PyTorch/TensorFlow/DeepSpeed/vLLM binding.

这是最软也最硬的锁。英伟达真城堡不是裸 die，是 20 年 × 590 万开发者 × 900+ 库 × PyTorch/TF/DeepSpeed/vLLM 一级原生。

Domestic side in 2026:

CANN: <1M devs, 3500 monthly active open-source contributors, 80% model-coverage inside China, ~1% of CUDA’s global footprint.
MUSA / MXMACA / DTK: 90–95% CUDA API translation for happy-path kernels, but MoE routing, mixed-precision training, comm-collectives, distributed parallel — the industrial-grade 10% — still OOMs or drifts.
Customers don’t buy TFLOPS, they buy “my pretrain finishes tomorrow.” Ecosystem migration cost > hardware price gap. That is why frontier-training clusters still leak back to import cards.

客户买的不是 TFLOPS，是“明天训练能跑完”。生态迁移成本大于硬件差价——这就是高端训练集群仍回流入口卡的根因。

III. The Chinese Counter-Strategy: System Beats Die

三、中国的反手：用系统打败单卡

Since the die cannot win alone, China fights at the datacenter-as-GPU layer.

单卡打不赢，就把“机房当一张卡”来打。

CloudMatrix 384: 384×910C as one super-node, beats GB200 NVL72 on aggregate bandwidth, 4× power. Trade electrons for sovereignty.
Chiplet proliferation: BR100, Siyuan 690, 950PR — multi-die masks the 7nm-vs-4nm gap by gluing small tiles with high-speed serdes-in-package.
Inference-first landing: 2026 domestic AI-accelerator share in China ≈ 60%, NVIDIA ≈ 8% — but mostly inference, fine-tune, vertical models. Frontier pretrain still bleeds.
Dual-track software: CUDA-translation (Hygon/MetaX/Moore) for fast porting + full-stack native (Ascend CANN/MindSpore, Cambricon NeuWare) for depth.
Hyperscaler in-house: Baidu Kunlun P800, Alibaba PPU (>A800, BOM −40% vs H20), ByteDance/Tencent silent silicon — clouds become fabs of code.

When you cannot shrink the transistor, shrink the problem.

缩不了晶体管，就缩问题本身。

IV. The Honest Verdict

四、老实话结论

Layer 层级	Domestic 2026 state 国产现状	Gap to B200 对 B200 代差
Logic process 逻辑制程	SMIC 7nm, 40–70% yield	2–3 nodes 2–3 代
HBM	CXMT HBM3 sample, HBM3E 2027	2–3 yrs 两三年
Advanced pkg 先进封装	2.5D OK, CoWoS-S large-reticle gap	yield & scale 良率/规模
EDA	analog OK, 7nm-down full-flow partial	3–5 yrs 三到五年
CUDA stack	80% China-scene, 10% global	10 yrs 十年级
Frontier pretrain 前沿训练	heterogeneous, not primary	1–2 gens 一到二代

So the precise sentence is:

China can design a flagship GPU, cannot yet mass-produce a B200-class one because EUV + HBM3E + CoWoS + CUDA-stack form a coupled lock; the unlock path is Chiplet + domestic 7nm + self-packaging + CUDA-translation + inference-first, accepting 1–2 generation deficit in frontier training while winning the inference and sovereign-cloud war.

精确说法是：

中国设计得出旗舰 GPU，但还无法量产 B200 级“高品质可量产卡”，因为 EUV + HBM3E + CoWoS + CUDA 栈是耦合锁；解锁路径是 Chiplet + 国产 7nm + 自研封装 + CUDA 翻译层 + 推理优先，接受前沿训练 1–2 代差，先在推理与主权云打赢。

V. Closing — Silicon Is a Language

五、收尾：硅是一种语言

The West built GPUs as commerce. China is forced to build them as sovereignty. The first produces CUDA. The second produces CANN, MUSA, MXMACA, NeuWare, DTK — fragmented today, convergent tomorrow.

西方造 GPU 是生意，中国造 GPU 是主权。前者长出 CUDA，后者长出 CANN/MUSA/MXMACA/NeuWare/DTK——今天碎片，明天收敛。

A high-quality GPU is not a chip. It is a sentence spoken by a thousand engineers in silicon, repeated by a million programmers in Python. Until that sentence is bilingual, “replacement” is a verb, not a state.

高品质 GPU 不是一颗芯片，而是上千工程师用硅说的一句话、百万程序员用 Python 复读的一句话。在这句话变成双语之前，“替代”是动词，不是状态。

The age of AI will not be won by the country with the smallest transistor.

It will be won by the country whose programmers forget they ever needed another’s stack.

AI 时代不属于晶体管最小的国家，属于程序员忘了自己曾需要别人栈的国家。

Field notes: WAIC 2026 floor, SMIC yield sheets, CXMT HBM roadmap, SemiAnalysis CUDA-vs-CANN dev-base model, 2026-08.

继续阅读：芯片 AI 中国 GPU 国产替代英伟达制程 EUV H100 B200 HBM EDA CUDA

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